Semiconductor package

ABSTRACT

A semiconductor package includes a first semiconductor chip on a package substrate, a second semiconductor chip on the first semiconductor chip and having a redistribution layer on a bottom surface thereof, under-bump pads on a bottom surface of the redistribution layer, first solders adjacent to the first semiconductor chip and connecting first pads of the under-bump pads to substrate pads of the package substrate, and a molding layer on the package substrate and covering the first and second semiconductor chips and the first solders. Second pads of the under-bump pads are in direct contact with a top surface of the first semiconductor chip. The first pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip. The second pads are insulated from the integrated circuit of the second semiconductor chip.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2021-0099837 filed on Jul. 29,2021 in the Korean Intellectual Property Office, the disclosure of whichis hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor package and amethod of fabricating the same.

Portable devices have been increasingly demanded in recent electronicproduct markets, and as a result, it has been ceaselessly required forreduction in size and weight of electronic parts mounted on the portabledevices. In particular, there is a continuous increase in need forexcellent performance memory devices, and it is required to achieve highbandwidth or high processing capacity.

In order to accomplish the reduction in size and weight of theelectronic parts, there is need for technology to integrate a number ofindividual devices into a single package as well as technology to reduceindividual sizes of mounting parts. In particular, semiconductorpackages operated at high frequency signals are required to havecompactness and excellent electrical characteristics.

In general, a TSV process, a flip chip process, and a wire bondingprocess may be employed to stack a plurality of memory chips on apackage substrate. However, there is a problem that the TSV process maybe complex and excessively expensive,.

SUMMARY

Some example embodiments of the present inventive concepts provide asemiconductor package with improved structural stability.

Some example embodiments of the present inventive concepts provide asemiconductor package with increased electrical properties.

Some example embodiments of the present inventive concepts provide acompact-sized semiconductor package.

Some example embodiments of the present inventive concepts provide asemiconductor package having memory chips stacked on a packagesubstrate, there the memory chips may be so stacked with reducedcomplexity and costs in relation to complexity and costs associated witha TSV process.

Some example embodiments of the present inventive concepts provide amethod of fabricating a semiconductor package according to any of theexample embodiments. Such a method may address complexity of processesto stack a plurality of memory chips on a package substrate and mayprovide a semiconductor package having memory chips stacked on a packagesubstrate with reduced complexity and costs in relation to complexityand costs associated with a TSV process.

According to some example embodiments of the present inventive concepts,a semiconductor package may comprise: a first semiconductor chip on apackage substrate; a second semiconductor chip on the firstsemiconductor chip, the second semiconductor chip having aredistribution layer on a bottom surface of the second semiconductorchip; a plurality of under-bump pads on a bottom surface of theredistribution layer; a plurality of first solders adjacent to the firstsemiconductor chip, the first solders connecting a plurality of firstpads of the under-bump pads to a plurality of substrate pads of thepackage substrate; and a molding layer on the package substrate, themolding layer covering the first semiconductor chip, the secondsemiconductor chip, and the first solders. A plurality of second pads ofthe under-bump pads may be in direct contact with a top surface of thefirst semiconductor chip. The first pads may be connected through theredistribution layer to an integrated circuit of the secondsemiconductor chip. The second pads may be insulated from the integratedcircuit of the second semiconductor chip.

According to some example embodiments of the present inventive concepts,a semiconductor package may comprise: a package substrate; a firstsemiconductor chip and a second semiconductor chip that are sequentiallystacked on the package substrate; a molding layer on the packagesubstrate, the molding layer covering the first semiconductor chip andthe second semiconductor chip; and a plurality of external terminals ona bottom surface of the package substrate. The second semiconductor chipmay be offset from the first semiconductor chip in a horizontaldirection that is parallel to at least a top surface of the packagesubstrate to vertically overlap a first lateral surface and a secondlateral surface of the first semiconductor chip. The first and secondlateral surfaces may be adjacent to each other. The first semiconductorchip may be mounted on the package substrate through a plurality offirst solders on the bottom surface of the first semiconductor chip suchthat the plurality of first solders are between the first semiconductorchip and the package substrate. The second semiconductor chip may bemounted on the package substrate through a plurality of second solderson the package substrate such that the plurality of second solders arebetween the second semiconductor chip and the package substrate. Thesecond solders may be adjacent to the first lateral surface and thesecond lateral surface of the first semiconductor chip and may be spacedapart from the first semiconductor chip. The second semiconductor chipmay be supported on a top surface of the first semiconductor chip.

According to some example embodiments of the present inventive concepts,a semiconductor package may comprise: a substrate; a first semiconductorchip that is flip-chip mounted on the substrate; a second semiconductorchip on the first semiconductor chip and horizontally offset from thefirst semiconductor chip in a horizontal direction that is parallel toat least a top surface of the substrate; a redistribution layer on abottom surface of the second semiconductor chip and connected to anintegrated circuit of the second semiconductor chip; a dummy pad betweenthe first semiconductor chip and the second semiconductor chip and on abottom surface of the redistribution layer; a signal pad on one side ofthe first semiconductor chip and on the bottom surface of theredistribution layer; a connection terminal on the one side of the firstsemiconductor chip and between the substrate and the secondsemiconductor chip; and a molding layer on the substrate and coveringthe first semiconductor chip and the second semiconductor chip, themolding layer filling a space between the substrate and the firstsemiconductor chip and a space between the substrate and the secondsemiconductor chip. The connection terminal may directly connect thesignal pad to a substrate pad of the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts.

FIGS. 2 and 3 illustrate enlarged cross-sectional views showing sectionA of FIG. 1 .

FIG. 4 illustrates a plan view showing redistribution by aredistribution layer of a second semiconductor chip.

FIG. 5 illustrates a plan view showing an arrangement of a firstsemiconductor chip and a second semiconductor chip.

FIG. 6 illustrates a plan view showing redistribution by aredistribution layer of a second semiconductor chip.

FIGS. 7, 8, and 9 illustrate plan views showing an arrangement of afirst semiconductor chip and a second semiconductor chip.

FIG. 10 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts.

FIGS. 11 and 12 illustrate plan views showing an arrangement of viaholes.

FIGS. 13, 14, and 15 illustrate cross-sectional views showing asemiconductor package according to some example embodiments of thepresent inventive concepts.

FIGS. 16, 17, 18, 19, 20, 21, and 22 illustrate cross-sectional viewsshowing a method of fabricating a semiconductor package according tosome example embodiments of the present inventive concepts.

DETAILED DESCRIPTION

The following will now describe a semiconductor package according to thepresent inventive concepts with reference to the accompanying drawings.

In the description of FIGS. 1 to 22 , the same reference numerals areused for substantially the same components, and duplicate descriptionsof the corresponding components will be omitted. Also, similar referencenumerals are used for similar components throughout various drawings ofthe present inventive concepts.

It will be understood that when an element such as a layer, film,region, or substrate is referred to as being “on” another element, itmay be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present. It willfurther be understood that when an element is referred to as being “on”another element, it may be above or beneath or adjacent (e.g.,horizontally adjacent) to the other element.

It will be understood that elements and/or properties thereof (e.g.,structures, surfaces, directions, or the like), which may be referred toas being “perpendicular,” “parallel,” “coplanar,” or the like withregard to other elements and/or properties thereof (e.g., structures,surfaces, directions, or the like) may be “perpendicular,” “parallel,”“coplanar,” or the like or may be “substantially perpendicular,”“substantially parallel,” “substantially coplanar,” respectively, withregard to the other elements and/or properties thereof.

Elements and/or properties thereof (e.g., structures, surfaces,directions, or the like) that are “substantially perpendicular” withregard to other elements and/or properties thereof will be understood tobe “perpendicular” with regard to the other elements and/or propertiesthereof within manufacturing tolerances and/or material tolerancesand/or have a deviation in magnitude and/or angle from “perpendicular,”or the like with regard to the other elements and/or properties thereofthat is equal to or less than 10% (e.g., a. tolerance of ±10%).

Elements and/or properties thereof (e.g., structures, surfaces,directions, or the like) that are “substantially parallel” with regardto other elements and/or properties thereof will be understood to be“parallel” with regard to the other elements and/or properties thereofwithin manufacturing tolerances and/or material tolerances and/or have adeviation in magnitude and/or angle from “parallel,” or the like withregard to the other elements and/or properties thereof that is equal toor less than 10% (e.g., a. tolerance of ±10%).

Elements and/or properties thereof (e.g., structures, surfaces,directions, or the like) that are “substantially coplanar” with regardto other elements and/or properties thereof will be understood to be“coplanar” with regard to the other elements and/or properties thereofwithin manufacturing tolerances and/or material tolerances and/or have adeviation in magnitude and/or angle from “coplanar,” or the like withregard to the other elements and/or properties thereof that is equal toor less than 10% (e.g., a. tolerance of ±10%)).

It will be understood that elements and/or properties thereof may berecited herein as being “the same” or “equal” as other elements, and itwill be further understood that elements and/or properties thereofrecited herein as being “identical” to, “the same” as, or “equal” toother elements may be “identical” to, “the same” as, or “equal” to or“substantially identical” to, “substantially the same” as or“substantially equal” to the other elements and/or properties thereof.Elements and/or properties thereof that are “substantially identical”to, “substantially the same” as or “substantially equal” to otherelements and/or properties thereof will be understood to includeelements and/or properties thereof that are identical to, the same as,or equal to the other elements and/or properties thereof withinmanufacturing tolerances and/or material tolerances. Elements and/orproperties thereof that are identical or substantially identical toand/or the same or substantially the same as other elements and/orproperties thereof may be structurally the same or substantially thesame, functionally the same or substantially the same, and/orcompositionally the same or substantially the same.

It will be understood that elements and/or properties thereof describedherein as being “substantially” the same and/or identical encompasseselements and/or properties thereof that have a relative difference inmagnitude that is equal to or less than 10%. Further, regardless ofwhether elements and/or properties thereof are modified as“substantially,” it will be understood that these elements and/orproperties thereof should be construed as including a manufacturing oroperational tolerance (e.g., ±10%) around the stated elements and/orproperties thereof.

When the terms “about” or “substantially” are used in this specificationin connection with a numerical value, it is intended that the associatednumerical value include a tolerance of ±10% around the stated numericalvalue. When ranges are specified, the range includes all valuestherebetween such as increments of 0.1%.

FIG. 1 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts. FIGS. 2 and 3 illustrate enlarged cross-sectional viewsshowing section A of FIG. 1 . FIG. 4 illustrates a plan view showingredistribution by a redistribution layer of a second semiconductor chip.FIG. 5 illustrates a plan view showing an arrangement of a firstsemiconductor chip and a second semiconductor chip.

Referring to FIGS. 1 and 2 , a package substrate 100 may be provided.The package substrate 100 may be a redistribution substrate. Forexample, the package substrate 100 may include one or more substratewiring layers that are stacked on each other. Each of the substratewiring layers may include a substrate dielectric layer 110 and asubstrate wiring pattern 120 in the substrate dielectric layer 110. Thesubstrate wiring pattern 120 of one of the substrate wiring layers maybe electrically connected to the substrate wiring pattern 120 of aneighboring substrate wiring layer.

The substrate dielectric layer 110 may include a dielectric polymer or aphoto-imageable dielectric (PID) polymer. For example, thephoto-imageable dielectric polymer may include one or more ofphotosensitive polyimide, polybenzoxazole (PBO), phenolic polymers, andbenzocyclobutene polymers.

The substrate wiring pattern 120 may be provided in the substratedielectric layer 110. The substrate wiring pattern 120 may horizontallyextend in the substrate dielectric layer 110. For example, the substratewiring pattern 120 may be one of a pad part and a line part of thesubstrate wiring layer. In such cases, the substrate wiring pattern 120may be a component for horizontal redistribution in the packagesubstrate 100. The substrate wiring pattern 120 may be provided on anupper portion of the substrate dielectric layer 110. The substratewiring pattern 120 may have a top surface that is exposed on a topsurface of the substrate dielectric layer 110. The substrate wiringpattern 120 provided at an uppermost substrate wiring layer may serve asa substrate pad coupled to one of a first semiconductor chip 200 and afirst connection terminal 380 which will be discussed below. Thesubstrate wiring pattern 120 may include a conductive material. Forexample, the substrate wiring pattern 120 may include metal, such ascopper (Cu).

The substrate wiring pattern 120 may have a via that protrudes onto abottom surface thereof. The via may be a component for verticalconnection between the substrate wiring patterns 120 of neighboringsubstrate wiring layers. In some example embodiments, the via may be acomponent for connection between an external pad 130 and the substratewiring pattern 120 of a lowermost substrate wiring layer. For example,the via may be coupled from the bottom surface of the substrate wiringpattern 120 to the top surface of the substrate wiring pattern 120 of anunderlying another substrate wiring layer. In some example embodiments,the via may be coupled form the bottom surface of the substrate wiringpattern 120 through a lowermost substrate dielectric layer 110 to a topsurface of the external pad 130.

A plurality of external pads 130 may be provided on a bottom surface ofthe lowermost substrate wiring layer. The external pads 130 may beelectrically connected to the substrate wiring pattern 120. The externalpads 130 may serve as pads to which are coupled a plurality of externalterminals 150 which will be discussed below.

A substrate protection layer 140 may be provided. The substrateprotection layer 140 may cover the bottom surface of the lowermostsubstrate wiring layer and expose the external pads 130. The externalpads 130 may be provided with external terminals 150 on exposed bottomsurfaces thereof. The external terminals 150 may include a solder ballor a solder bump.

The package substrate 100 may be configured as discussed above. Thepresent inventive concepts, however, are not limited thereto. Thepackage substrate 100 may be a printed circuit board (PCB). For example,the package substrate 100 may have a core portion layer and peripheralparts for connection between lines on top and bottom portions of thecore portion layer.

A first semiconductor chip 200 may be disposed on the package substrate100. The first semiconductor chip 200 may have a front surface and arear surface. In this description below, a front surface may be definedto refer to a surface at an active surface side on which is formed anintegrated element of a semiconductor chip, and a rear surface may bedefined to refer to another surface opposite to the front surface. Forexample, the first semiconductor chip 200 may include first chip pads216 provided on the front surface of the first semiconductor chip 200.The first semiconductor chip 200 may have a first lateral surface 200 aand a second lateral surface 200 b that are opposite to each other in afirst direction D1. Hereinafter, a first direction D1 and a seconddirection D2 are defined to each indicate a direction parallel to a topsurface of the package substrate 100, and a third direction D3 isdefined to indicate a direction perpendicular to the top surface of thepackage substrate 100. The first lateral surface 200 a may be a lateralsurface in the first direction D1 of the first semiconductor chip 200,and the second lateral surface 200 b may be a lateral surface of thefirst semiconductor chip 200 in a direction reverse to the firstdirection D1. The first semiconductor chip 200 may be a memory chip,such as dynamic random-access memory (DRAM), static random access memory(SRAM), magnetic random access memory (MRAM), or Flash memory. In someexample embodiments, the first semiconductor chip 200 may be a logicchip, a passive device, or any other suitable semiconductor chip. Thefirst semiconductor chip 200 may include a semiconductor material, suchas silicon (Si).

The first semiconductor chip 200 may have a first base layer 201 onwhich is formed a first integrated circuit 202 of the firstsemiconductor chip 200, and may also have a first chip wiring layer 210provided on one surface on which the first integrated circuit 202 isformed on the first base layer 201. The first chip wiring layer 210 mayinclude a first chip dielectric pattern 212, a first chip wiring pattern214 in the first chip dielectric pattern 212, first chip pads 216connected to the first chip wiring pattern 214, and a first chippassivation layer 213 that encapsulates the first chip wiring pattern214 on the first chip dielectric pattern 212 and exposes the first chippads 216.

The first chip dielectric pattern 212 may be disposed on a bottomsurface of the first base layer 201, covering the first integratedcircuit 202. The first chip dielectric pattern 212 may be provided inplural (e.g., the semiconductor package may include a plurality of firstchip dielectric patterns 212), and the plurality of first chipdielectric patterns 212 may be stacked on each other. In this case, thefirst chip dielectric patterns 212 may be wiring layers that arevertically connected to each other. The first chip dielectric patterns212 may include silicon oxide (SiO), silicon nitride (SiN), or siliconoxynitride (SiON).

The first chip pads 216 may be provided on a bottom surface of the firstchip dielectric pattern 212. The first chip pads 216 may be provided ona central portion of the first semiconductor chip 200. For example, thefirst chip pads 216 may be arranged in the second direction D2 on thecentral portion of the first semiconductor chip 200. The first chip pads216 may be arranged to constitute one column or two or more plurality ofcolumns. In addition, the first chip pads 216 may be arranged in ahoneycomb shape or a grid shape having a plurality of columns and rowsalong the first and second directions D1 and D2. In some exampleembodiments, the first chip pads 216 may be arranged at an irregularperiod. For example, the first chip pads 216 may be provided to have nospecific regularity. In this case, the first chip pads 216 may bevariously arranged depending on integration and/or positions of wiringlines in the first semiconductor chip 200. The first chip pads 216 mayinclude a metallic material, such as aluminum (Al).

The first chip wiring pattern 214 may be provided in the first chipdielectric pattern 212. The first chip wiring pattern 214 mayhorizontally extend in the first chip dielectric pattern 212. Forexample, the first chip dielectric pattern 212 may be a component forhorizontal redistribution of the first integrated circuit 202 in thefirst semiconductor chip 200. The first chip dielectric pattern 212 mayconnect the first integrated circuit 202 to the first chip pads 216.FIG. 1 depicts that the first chip wiring pattern 214 is illustrated asan arbitrary solid line to indicate connections between the firstintegrated circuit 202 and the first chip pads 216, but in the presentinventive concepts, a shape or electrical connection of the first chipwiring pattern 214 is not limited to that shown in FIG. 1 .

The first chip passivation layer 213 may be provided on the bottomsurface of the first chip dielectric pattern 212. The first chippassivation layer 213 may cover the first chip pads 216 on the bottomsurface of the first chip dielectric pattern 212, and may have openingsthat expose portions of bottom surfaces of the first chip pads 216. Thefirst chip passivation layer 213 may include a photosensitive polymer,such as polyimide.

The first semiconductor chip 200 may be flip-chip mounted on the packagesubstrate 100. For example, the first semiconductor chip 200 may beplaced to allow the first chip pads 216 to face the package substrate100. In this case, the first semiconductor chip 200 may be placed toallow its front surface to face the package substrate 100. A pluralityof first chip terminals 220 may be provided between the packagesubstrate 100 and the first chip pads 216. The first chip terminals 220may penetrate the first chip passivation layer 213 and may be coupled tothe first chip pads 216. For example, in the openings of the first chippassivation layer 213, the first chip terminals 220 may be coupled tothe first chip pads 216. The first semiconductor chip 200 may beconnected to the package substrate 100 through the first chip pads 216,the first chip terminals 220, and the substrate wiring pattern 120. Thefirst chip terminals 220 may include a solder ball or a solder bump.

A second semiconductor chip 300 may be disposed on the firstsemiconductor chip 200. The second semiconductor chip 300 may bedisposed on the rear surface of the first semiconductor chip 200. Thesecond semiconductor chip 300 and the first semiconductor chip 200 maybe disposed in an offset stack structure. For example, the firstsemiconductor chip 200 and the second semiconductor chip 300 may bestacked obliquely in the first direction D1, which may result in anascending stepwise shape. For example, a portion of the secondsemiconductor chip 300 may overlap the first semiconductor chip 200, andanother portion of the second semiconductor chip 300 may protrude onto acertain lateral surface of the first semiconductor chip 200. The secondsemiconductor chip 300 may protrude onto the first lateral surface 200 aof the first semiconductor chip 200. For example, when viewed in a planview, the second semiconductor chip 300 may be stacked on the firstsemiconductor chip 200 such that the second semiconductor chip 300 maybe shifted in the first direction D1 from the first semiconductor chip200 (e.g., the second semiconductor chip 300 may be offset from thefirst semiconductor chip 200 in a horizontal direction that is parallelto at least a top surface of the package substrate 100, or the like,such as the first direction D1), such that the second semiconductor chip300 may vertically overlap (e.g., overlap in the third direction D3) thefirst lateral surfaces 200 a of the first semiconductor chip 200 and maynot vertically overlap the second lateral surface 200 b of the firstsemiconductor chip 200. A front surface, or a bottom surface, of thesecond semiconductor chip 300 may be parallel or substantially parallelto the top surface of the package substrate 100.

The second semiconductor chip 300 may be configured identical orsubstantially identical or similar to the first semiconductor chip 200.For example, the second semiconductor chip 300 may be of the same typeas the first semiconductor chip 200. For example, the secondsemiconductor chip 300 may be a memory chip, such as dynamicrandom-access memory (DRAM), static random access memory (SRAM),magnetic random access memory (MRAM), or Flash memory. In some exampleembodiments, the second semiconductor chip 300 may be a logic chip, apassive device, or any other suitable semiconductor chip. The secondsemiconductor chip 300 may include a semiconductor material, such assilicon (Si). The second semiconductor chip 300 may include a secondbase layer 301 in which is formed a second integrated circuit 302 of thesecond semiconductor chip 300, and may also include a second chip wiringlayer 310 provided on one surface on which the second integrated circuit302 is formed in the second base layer 301. The second chip wiring layer310 may include a second chip dielectric pattern 312, a second chipwiring pattern 314 in the second chip dielectric pattern 312, secondchip pads 316 connected to the second chip wiring pattern 314, and asecond chip passivation layer 313 that covers the second chip wiringpattern 314 on the second chip dielectric pattern 312 and exposes thesecond chip pads 316.

On a bottom surface of the second base layer 301, the second chipdielectric pattern 312 may cover the second integrated circuit 302. Thesecond chip dielectric pattern 312 may be provided in plural (e.g., thesemiconductor package may include a plurality of second chip dielectricpatterns 312), and the plurality of second chip dielectric patterns 312may be stacked on each other. In this case, the second chip dielectricpatterns 312 may be wiring layers that are vertically connected to eachother. The second chip dielectric patterns 312 may include silicon oxide(SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

The second chip pads 316 may be provided on a bottom surface of thesecond chip dielectric pattern 312. The second chip pads 316 may beprovided on a central portion of the second semiconductor chip 300. Forexample, as shown in FIG. 4 , the second chip pads 316 may be arrangedin the second direction D2 on the central portion of the secondsemiconductor chip 300. FIG. 4 depicts that the second chip pads 316constitute three columns along the second direction D2, but the presentinventive concepts are not limited thereto. The second chip pads 316 maybe arranged to constitute one column, two columns, or four or morecolumns. In addition, the second chip pads 316 may be arranged in ahoneycomb shape or a grid shape having a plurality of columns and rowsalong the first and second directions D1 and D2. In some exampleembodiments, the second chip pads 316 may be arranged at an irregularperiod. For example, the second chip pads 316 may be provided to have nospecific regularity. In this case, the second chip pads 316 may bevariously arranged depending on integration and/or positions of lines inthe second semiconductor chip 300. The second chip pads 316 may includea metallic material, such as aluminum (Al).

The second chip wiring pattern 314 may be provided in the second chipdielectric pattern 312. The second chip wiring pattern 314 mayhorizontally extend in the second chip dielectric pattern 312. Forexample, the second chip dielectric pattern 312 may be a component forhorizontal redistribution of the second integrated circuit 302 in thesecond semiconductor chip 300. The second chip dielectric pattern 312may connect the second integrated circuit 302 to the second chip pads316. FIG. 1 depicts that the second chip wiring pattern 314 isillustrated as an arbitrary solid line to indicate connections betweenthe second integrated circuit 302 and the second chip pads 316, but inthe present inventive concepts, a shape or electrical connection of thesecond chip wiring pattern 314 is not limited to that shown in FIG. 1 .

The second chip passivation layer 313 may be provided on the bottomsurface of the second chip dielectric pattern 312. The second chippassivation layer 313 may cover the second chip pads 316 on the bottomsurface of the second chip dielectric pattern 312, and may have openingsthat expose portions of bottom surfaces of the second chip pads 316. Thesecond chip passivation layer 313 may include a photosensitive polymer,such as polyimide.

The second semiconductor chip 300 may be disposed to allow the secondchip pads 316 to face the package substrate 100. In this case, thesecond semiconductor chip 300 may be placed to allow its front surfaceto face the package substrate 100. The second semiconductor chip 300 maybe a memory chip. In some example embodiments, the second semiconductorchip 300 may be a logic chip, a passive device, or any other suitablesemiconductor chip. The second semiconductor chip 300 may include asemiconductor material, such as silicon (Si). The second semiconductorchip 300 may have a thickness the same as that of the firstsemiconductor chip 200. For example, a distance between a top surface ofthe second base layer 301 and bottom surfaces of the second chip pads316 may be the same as a distance between a top surface of the firstbase layer 201 and bottom surfaces of the first chip pads 216.

The second semiconductor chip 300 may further include a firstredistribution layer 350 provided on the front surface of the secondsemiconductor chip 300. For example, the first redistribution layer 350may be provided on the bottom surface of the second semiconductor chip300, and may cover the second base layer 301 and the second chip wiringlayer 310. The first redistribution layer 350 may include a firstdielectric pattern 352 stacked on the bottom surface of the secondsemiconductor chip 300, a first wiring pattern 354 provided in the firstdielectric pattern 352, and first signal pads 356 and first dummy pads358 exposed on a bottom surface of the first redistribution layer 350.

The first dielectric pattern 352 may cover a bottom surface of thesecond chip wiring layer 310. The first dielectric pattern 352 mayinclude a plurality of dielectric layers that are stacked on each other.The first dielectric pattern 352 may include a dielectric material. Forexample, the first dielectric pattern 352 may include a dielectricpolymer. The first dielectric pattern 352 may include at least oneselected from photosensitive polyimide, polybenzoxazole (PBO), phenolicpolymers, and benzocyclobutene polymers.

The first signal pads 356 and the first dummy pads 358 may be providedbelow the first dielectric pattern 352. The first signal pads 356 andthe first dummy pads 358 may be exposed on a bottom surface of the firstdielectric pattern 352. In this case, the first signal pads 356 and thefirst dummy pads 358 may extend or protrude onto the bottom surface ofthe first dielectric pattern 352. For example, each of the first signalpads 356 and the first dummy pads 358 may have a portion that ispositioned on the bottom surface of the first dielectric pattern 352,and may also have another portion that penetrates the first dielectricpattern 352 and are connected to the first wiring pattern 354 in thefirst dielectric pattern 352. In some example embodiments, the firstsignal pads 356 and the first dummy pads 358 may have their bottomsurfaces coplanar with the bottom surface of the first dielectricpattern 352. The bottom surfaces of the first signal pads 356 and of thefirst dummy pads 358 may be located at the same level as that of the topsurface of the package substrate 100. The first signal pads 356 and thefirst dummy pads 358 may be under-bump pads that are exposed on alowermost surface of the first redistribution layer 350. The firstsignal pads 356 may be connection pads for externally transceivingelectrical signals with the second integrated circuit 302 of the secondsemiconductor chip 300, and the first dummy pads 358 may be electricallyfloated from the second integrated circuit 302 of the secondsemiconductor chip 300. The first signal pads 356 and the first dummypads 358 may include a conductive material. For example, the firstsignal pads 356 and the first dummy pads 358 may include copper (Cu).

In the present specification, the term ‘level’ may mean a verticalheight and/or a distance from a reference location (e.g., the bottomsurface of the first semiconductor chip 200, the bottom surface of thesecond semiconductor chip 300, the top surface of the package substrate100, or the like) in a vertical direction (e.g., the third directionD3). A reference location may be understood to be a location that alevel and/or relative level of an element is “based on” or is a level“from.” For example, when a first element is described herein to be at alevel from a reference location that is higher than a second element,the first element may be further from the reference location in thevertical direction (e.g., third direction D3) than the second element.In another example, when a first element is described herein to be at alevel from a reference location that is lower than a second element, thefirst element may be closer to reference location in the verticaldirection (e.g., third direction D3) than the second element. In anotherexample, when a first element is described herein to be at a same orsubstantially same level from a reference location as a second element,the first element may be equally distant from/close to the referencelocation in the vertical direction (e.g., third direction D3) as thesecond element.

FIG. 4 depicts the bottom surface of the second semiconductor chip 300,and for convenience of description, FIG. 4 also depicts positions of thesecond chip pads 316 in the second semiconductor chip 300.

Referring to FIGS. 1 to 4 , the second semiconductor chip 300 may have afirst region RG1 and a second region RG2. The first region RG1 may bepositioned in the first direction D1 of the second region RG2. Whenviewed in a plan view, the first region RG1 of the second semiconductorchip 300 may be positioned on one side in the first direction D1 of thefirst semiconductor chip 200, and the second region RG2 of the secondsemiconductor chip 300 may be positioned on the first semiconductor chip200. The first region RG1 of the second semiconductor chip 300 may bedefined to refer to an area where the first signal pads 356 areprovided, and the second region RG2 of the second semiconductor chip 300may be defined to refer to an area where the first dummy pads 358 areprovided.

The first signal pads 356 may be disposed on the first region RG1 on thefront surface of the second semiconductor chip 300. The first signalpads 356 may constitute at least one column that extends along the firstlateral surface 200 a of the first semiconductor chip 200 on the firstregion RG1. For example, the first signal pads 356 may constitute atleast one column that extends along the second direction D2 on the firstregion RG1. When viewed in a plan view, each of the first signal pads356 may be spaced apart from (e.g., isolated from direct contact with)the first semiconductor chip 200. FIG. 4 depicts that the first signalpads 356 constitute three columns, but the present inventive conceptsare not limited thereto. The first signal pads 356 may constitute onecolumn, two columns, or four or more plurality of columns. A pluralityof columns constituted by the first signal pads 356 may be spaced apartfrom each other in the first direction D1.

The first dummy pads 358 may be disposed on the front surface of thesecond semiconductor chip 300 on the second region RG2. The first dummypads 358 may constitute at least one column that extends along thesecond direction D2 on the second region RG2. Each of the first dummypads 358 may vertically overlap the first semiconductor chip 200 (e.g.,overlap the first semiconductor chip 200 in the third direction D3).FIG. 4 depicts that the first dummy pads 358 constitute two columns, butthe present inventive concepts are not limited thereto. The first dummypads 358 may constitute one column or three or more plurality ofcolumns. A plurality of columns that are constituted by the first dummypads 358 may be spaced apart from each other in the first direction D1.FIG. 4 depicts that the first dummy pads 358 are arranged along thesecond direction D2, but the present inventive concepts are not limitedthereto. An arrangement of the first dummy pads 358 may be variouslychanged based on positions and weights of the first semiconductor chip200 and the second semiconductor chip 300.

The first wiring pattern 354 may be provided within the first dielectricpattern 352. The first wiring pattern 354 may be coupled to the secondchip pads 316 after penetrating the second chip passivation layer 313 ofthe second chip wiring layer 310, and may electrically connect thesecond chip pads 316 to the first signal pads 356 The second chip wiringlayer 310 and the first wiring pattern 354 may cause the secondintegrated circuit 302 of the second semiconductor chip 300 to haveelectrical connection with the first signal pads 356. For example, asshown in FIG. 4 , the first redistribution layer 350 may have a windowregion WRG positioned on a top surface thereof. The window region WRGmay extend in the second direction D2 on a central portion of the firstredistribution layer 350. When viewed in a plan view, the window regionWRG may the same as an area where the second chip pads 316 are disposed,and the area may be defined to indicate a section where the first wiringpattern 354 and the second chip pads 316 are coupled at an interfacebetween the first redistribution layer 350 and the second chip wiringlayer 310. For example, on the window region WRG, the first wiringpattern 354 may be exposed on a top surface of the first dielectricpattern 352 or the top surface of the first redistribution layer 350,and the exposed first wiring pattern 354 may be in contact (e.g., indirect contact) with the second chip pads 316. The first signal pads 356may be arranged in the second direction D2 on one side in the firstdirection D1 of the window region WRG. In this case, ones of the firstsignal pads 356 may overlap the window region WRG. FIG. 4 depicts that aboundary between the first and second regions RG1 and RG2 overlaps thewindow region WRG, but the present inventive concepts are not limitedthereto. In addition, FIG. 4 depicts that the first wiring pattern 354is illustrated as an arbitrary solid line to indicate connectionsbetween the first signal pads 356 and the second chip pads 316. As shownin FIG. 2 , the first wiring pattern 354 may be electrically insulatedfrom the first dummy pads 358. For example, the first dummy pads 358 maybe positioned on the bottom surface of the first dielectric pattern 352,and the first dielectric pattern 352 may separate the first dummy pads358 from the first wiring pattern 354. The second integrated circuit 302of the second semiconductor chip 300 may be electrically insulated fromthe first dummy pads 358. Accordingly, the first dummy pads 358 may beinsulated from the second integrated circuit 302 of the secondsemiconductor chip 300, for example by at least the first dielectricpattern 352. In some example embodiments, as shown in FIG. 3 , portionsof the first wiring pattern 354 may be connected to the first dummy pads358. In this case, the portions of the first wiring pattern 354connected to the first dummy pads 358 may be electrically floated fromthe second chip pads 316. Therefore, the second integrated circuit 302of the second semiconductor chip 300 may be electrically insulated fromthe first dummy pads 358 based on the electric floating.

FIG. 5 roughly illustrates the bottom surface of the secondsemiconductor chip 300, and for convenience of description, FIG. 5 alsodepicts a position of the first semiconductor chip 200. In FIG. 5 , thesecond semiconductor chip 300 is seen from the bottom, and the firstsemiconductor chip 200 covers a portion of the bottom surface of thesecond semiconductor chip 300.

Referring to FIGS. 1 to 5 , the second semiconductor chip 300 may beflip-chip mounted on the package substrate 100. For example, firstconnection terminals 380 (also referred to herein as first solders) maybe provided between the first signal pads 356 (which may be referred toas a plurality of first pads of under-bump pads on a bottom surface ofthe first redistribution layer 350) and the package substrate 100 (e.g.,substrate wiring pattern 120 which may include a plurality of substratepads of the package substrate 100). The first dummy pads 358 may bereferred to as a plurality of second pads of the under-bump pads thatare in direct contact with a top surface of the first semiconductor chip200. The first signal pads 356 may be connected through the firstredistribution layer 350 to an integrated circuit of the secondsemiconductor chip 300. The second semiconductor chip 300 may beconnected to the package substrate 100 through the first signal pads356, the first connection terminals 380, and the substrate wiringpattern 120. The first connection terminals 380 may be disposed on oneside in the first direction D1 of the first semiconductor chip 200(e.g., adjacent to the first semiconductor chip 200). For example, thefirst connection terminals 380 may be disposed adjacent to the firstlateral surface 200 a of the first semiconductor chip 200. The firstconnection terminals 380 may be correspondingly provided on the firstsignal pads 356. An arrangement of the first connection terminals 380may conform to that of the first signal pads 356. For example, the firstconnection terminals 380 may constitute at least one column that extendsalong the second direction D2. The first connection terminals 380 may becoupled to the substrate wiring pattern 120 of the package substrate100. Therefore, the second integrated circuit 302 of the secondsemiconductor chip 300 may be electrically connected to the packagesubstrate 100 through the first redistribution layer 350, the firstsignal pads 356, and the first connection terminals 380. The firstconnection terminals 380 may have their top surfaces located at a levelfrom the package substrate 100 the same as that of a top surface of thefirst semiconductor chip 200. In some example embodiments, the topsurfaces of the first connection terminals 380 may be located at a levelfrom the package substrate 100 different from that of the top surface ofthe first semiconductor chip 200. The first connection terminals 380 mayhave a first height that is about 1.5 times to about 30 times a secondheight of the first chip terminals 220. For example, the first height ofthe first connection terminals 380 may range from about 50 μm to about300 μm, and the second height of the first chip terminals 220 may rangefrom about 10 μm to about 50 μm. The first connection terminals 380 mayinclude a solder ball or a solder bump. For example, the firstconnection terminals 380 may be solder balls each having a compositestructure that includes a core portion 382 (e.g., solder core portion)formed of metal and a peripheral portion 384 (e.g., solder peripheralportion) surrounding the core portion 382. According to some exampleembodiments, the first connection terminals 380 may include one of aconductive post, a vertical via, and any other suitable connectionterminal each of which is coupled to the substrate wiring pattern 120 ofthe package substrate 100.

The first dummy pads 358 of the second semiconductor chip 300 may be incontact (e.g., in direct contact) with the top surface of the firstsemiconductor chip 200. For example, the first dummy pads 358 may beprovided between the bottom surface of the second semiconductor chip 300and the top surface of the first semiconductor chip 200. On the topsurface of the first semiconductor chip 200, the first dummy pads 358may support the second semiconductor chip 300. The first dummy pads 358may be in direct contact with the top surface of the first semiconductorchip 200 or the top surface of the first base layer 201.

According to some example embodiments of the present inventive concepts,as the first and second semiconductor chips 200 and 300 are disposed tovertically overlap each other, the first and second semiconductor chips200 and 300 may have a reduced occupying planar area and a compact-sizedsemiconductor package may be provided. The first redistribution layer350 may redistribute the second semiconductor chip 300 to allow thefirst signal pads 356 to line on one side of the second semiconductorchip 300. Therefore, a semiconductor package may be formed to have alarge overlapping area between the second semiconductor chip 300 and thefirst semiconductor chip 200, and may decrease in planar area. Forexample, even when the first semiconductor chip 200 is provided thereonwith the window region WRG on which are provided the second chip pads316 of the second semiconductor chip 300, the first redistribution layer350 may cause an electrical connection of the second semiconductor chip300 to extend toward one side of the first semiconductor chip 200 andmay easily mount the second semiconductor chip 300 on the packagesubstrate 100. Therefore, a semiconductor package may become small insize.

In addition, as the second semiconductor chip 300 is redistributed bythe first redistribution layer 350, it may be possible to increase thedegree of freedom of electrical connection for the second semiconductorchip 300. Moreover, the second semiconductor chip 300 may be directlyconnected to the package substrate 100, and thus there may be a reducedlength of electrical connection between the second semiconductor chip300 and the package substrate 100. Accordingly, a semiconductor packagemay increase in electrical properties.

Furthermore, the first dummy pads 358 may be used to support the secondsemiconductor chip 300 on the first semiconductor chip 200 (e.g., suchthat the second semiconductor chip 300 may be supported on a top surfaceof the first semiconductor chip 200 such that at least a portion of thestructural load or weight of the second semiconductor chip 300 isconfigured to be transferred to at least the first semiconductor chip200 via at least the top surface of the first semiconductor chip 200),and thus a semiconductor package may be provided to have improvedstructural stability. The first dummy pads 358 may be disposedregardless of wiring connection of the first semiconductor chip 200and/or regardless of wiring connection of the second semiconductor chip300, and an arrangement of the first dummy pads 358 may be variouslychanged based on shape and thickness of the second semiconductor chip300. Accordingly, the second semiconductor chip 300 may be stablysupported on the first semiconductor chip 200, and a semiconductorpackage may be provided to have improved structural stability.

Referring back to FIGS. 1 to 3 , a molding layer 400 may be provided onthe package substrate 100. The molding layer 400 may cover the packagesubstrate 100. On the package substrate 100, the molding layer 400 mayencapsulate the first connection terminals 380, the first semiconductorchip 200, and the second semiconductor chip 300. For example, themolding layer 400 may cover lateral and top surfaces of the firstsemiconductor chip 200 and lateral and top surfaces of the secondsemiconductor chip 300. Differently from that shown, the molding layer400 may expose the top surface of the second semiconductor chip 300. Onone side of the first semiconductor chip 200, the molding layer 400 mayfill a space between the package substrate 100 and the secondsemiconductor chip 300. The molding layer 400 may surround the firstconnection terminals 380 between the package substrate 100 and thesecond semiconductor chip 300. The molding layer 400 may contact lateralsurfaces of the first connection terminals 380. The molding layer 400may extend into a gap between the first semiconductor chip 200 and thepackage substrate 100, thereby encapsulating the first chip terminals220. The molding layer 400 may include a dielectric polymer, such as anepoxy molding compound (EMC).

FIG. 6 illustrates a plan view showing redistribution by aredistribution layer of a second semiconductor chip. FIGS. 7, 8, and 9illustrate plan views showing an arrangement of a first semiconductorchip and a second semiconductor chip. FIGS. 7 to 9 roughly illustratethe bottom surface of the second semiconductor chip 300, and forconvenience of description, FIGS. 7 to 9 also depict a position of thefirst semiconductor chip 200. In FIGS. 7 to 9 , the second semiconductorchip 300 is seen from the bottom, and the first semiconductor chip 200covers a portion of the bottom surface of the second semiconductor chip300.

Referring to FIGS. 1 to 3 and 6 , the second semiconductor chip 300 maybe disposed on the first semiconductor chip 200. The secondsemiconductor chip 300 may be positioned on the rear surface of thefirst semiconductor chip 200. The second semiconductor chip 300 and thefirst semiconductor chip 200 may be disposed in an offset stackstructure. For example, the first semiconductor chip 200 and the secondsemiconductor chip 300 may be stacked obliquely in the first and seconddirections D1 and D2, which may result in an ascending stepwise shape.As shown in FIG. 7 , the second semiconductor chip 300 may protrudebeyond the first lateral surface 200 a and a third lateral surface 200 cof the first semiconductor chip 200. The third lateral surface 200 c maybe a lateral surface in the second direction D2 of the firstsemiconductor chip 200 and may be a lateral surface in contact (e.g., indirect contact) with the first lateral surface 200 a and may beunderstood to be adjacent to the first lateral surface 200 a. Forexample, when viewed in a plan view, the second semiconductor chip 300may be stacked on the first semiconductor chip 200 such that the secondsemiconductor chip 300 may be shifted in the first and second directionsD1 and D2 from the first semiconductor chip 200. The secondsemiconductor chip 300 may vertically overlap the first and thirdlateral surfaces 200 a and 200 c of the first semiconductor chip 200,such that the second semiconductor chip 300 may vertically overlap(e.g., overlap in the third direction D3) the adjacent first and thirdlateral surfaces 200 a and 200 c of the first semiconductor chip 200.

As illustrated in FIG. 7 , the first lateral surface 200 a of the firstsemiconductor chip 200 may be positioned below the window region WRG ofthe second semiconductor chip 300. According to some exampleembodiments, the first and second semiconductor chips 200 and 300 may bedisposed to increase an overlapping area between the first and secondsemiconductor chips 200 and 300. For example, as shown in FIGS. 8 and 9, the first lateral surface 200 a of the first semiconductor chip 200may overlap the window region WRG of the second semiconductor chip 300,and when viewed in a plan view, may be positioned in the first directionD1 of the window region WRG.

The second semiconductor chip 300 may further include a firstredistribution layer 350 provided on the front surface of the secondsemiconductor chip 300. The first redistribution layer 350 may include afirst dielectric pattern 352 stacked on the bottom surface of the secondsemiconductor chip 300, a first wiring pattern 354 provided in the firstdielectric pattern 352, and first signal pads 356 and first dummy pads358 exposed on a bottom surface of the first redistribution layer 350.

The second semiconductor chip 300 may have a first region RG1′ and asecond region RG2′. The first region RG1′ may be positioned I the firstand second directions D1 and D2 of the second region RG2′. When viewedin a plan view, the first region RG1′ of the second semiconductor chip300 may be located on one side in the first direction D1 of the firstsemiconductor chip 200 and on one side in the second direction D2 of thefirst semiconductor chip 200, and the second region RG2′ of the secondsemiconductor chip 300 may be located on the first semiconductor chip200. For example, the first region RG1′ may surround the second regionRG2′ in the first and second directions D1 and D2.

The first signal pads 356 may be disposed on the first region RG1′ onthe front surface of the second semiconductor chip 300. The first signalpads 356 may constitute at least one column that extends along thesecond direction D2 on the first region RG1′. For example, the firstsignal pads 356 adjacent to the first lateral surface 200 a of the firstsemiconductor chip 200 may be arranged along the first lateral surface200 a of the first semiconductor chip 200 on one side in the firstdirection D1 of the window region WRG. When viewed in a plan view, thefirst signal pads 356 adjacent to the third lateral surface 200 c of thefirst semiconductor chip 200 may be arranged in the second direction D2on opposite sides in the first direction D1 of the window region WRG.

According to some example embodiments of the present inventive concepts,as the first signal pads 356 are disposed adjacent to the window regionWRG on which the second chip pads 316 are disposed, a reduced length maybe given to the first wiring pattern 354 that connects the first signalpads 356 to the second chip pads 316. As a result, a semiconductorpackage may have improved electrical properties.

The first dummy pads 358 may be disposed on the second region RG2′ onthe front surface of the second semiconductor chip 300. The first dummypads 358 may constitute at least one column that extends along thesecond direction D2 on the second region RG2′. The first dummy pads 358may constitute one column or three or more plurality of columns. Aplurality of columns that are constituted by the first dummy pads 358may be spaced apart from each other in the first direction D1.

Referring to FIGS. 1 to 3, 6, and 7 , the second semiconductor chip 300may be flip-chip mounted on the package substrate 100. For example,first connection terminals 380 may be provided between the first signalpads 356 and the package substrate 100. The first connection terminals380 may be disposed on one side in the first direction D1 of the firstsemiconductor chip 200 and on one side in the second direction D2 of thefirst semiconductor chip 200. For example, the first connectionterminals 380 may be located adjacent to the first and third lateralsurfaces 200 a and 200 c of the first semiconductor chip 200. The firstconnection terminals 380 may be correspondingly provided on the firstsignal pads 356. An arrangement of the first connection terminals 380may conform to that of the first signal pads 356. The first connectionterminals 380 may include a solder ball or a solder bump.

The first dummy pads 358 of the second semiconductor chip 300 may be incontact (e.g., in direct contact) with the top surface of the firstsemiconductor chip 200. For example, the first dummy pads 358 may beprovided between the bottom surface of the second semiconductor chip 300and the top surface of the first semiconductor chip 200. On the topsurface of the first semiconductor chip 200, the first dummy pads 358may support the second semiconductor chip 300.

As shown in FIGS. 8 and 9 , the first lateral surface 200 a of the firstsemiconductor chip 200 may be positioned in the first direction D1 ofthe window region WRG.

As illustrated in FIG. 8 , a distance between the window region WRG andthe first signal pads 356 may be less on the third lateral surface 200 cof the first semiconductor chip 200 than on the first lateral surface200 a of the first semiconductor chip 200. For example, the windowregion WRG may partially overlap the first semiconductor chip 200, and areduced length may be provided between the first signal pads 356 and thewindow region WRG that does not overlap the first semiconductor chip200. Therefore, a reduced length may be given to the first wiringpattern 354 that connects the first signal pads 356 to the second chippads 316, a semiconductor package may be provided to have improvedelectrical properties.

In some example embodiments, as illustrated in FIG. 9 , the first signalpads 356 may constitute at least one column that extends along the firstand third lateral surfaces 200 a and 200 c of the first semiconductorchip 200 on the first region RG1′. For example, the first signal pads356 adjacent to the first lateral surface 200 a of the firstsemiconductor chip 200 may be arranged along the second direction D2,and the first signal pads 356 adjacent to the third lateral surface 200c of the first semiconductor chip 200 may be arranged in the firstdirection D1. In this case, as the first signal pads 356 are arrangedaround the first semiconductor chip 200 and along the first and thirdlateral surfaces 200 a and 200 c of the first semiconductor chip 200,the first signal pads 356 may have high integration, and a semiconductorpackage may be provided to have a compact size and high integration.

FIG. 10 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts. FIGS. 11 and 12 illustrate plan views showing an arrangementof via holes.

Referring to FIG. 10 , the package substrate 100 may have vent holes VH1and VH2. For example, as shown in FIG. 10 , the package substrate 100may have inner surfaces 100S1 and 100S2 that respectively define thevent holes WH1 and VH2 extending through the thickness of the packagesubstrate 100 in the third direction D3. The vent holes VH1 and VH2 mayvertically penetrate the package substrate 100 to extend from the top tobottom surfaces of the package substrate 100. The vent holes VH1 and VH2may be provided on a central portion of the package substrate 100. Thevent holes VH1 and VH2 may include first vent holes VH1 provided belowthe first semiconductor chip 200 (e.g., vertically overlapping the firstsemiconductor chip 200 in the third direction D3 as shown in FIGS. 10-11) and second vent holes VH2 provided below the second semiconductor chip300 (e.g., vertically overlapping the second semiconductor chip 300 inthe third direction D3 as shown in FIGS. 10-11 ). The vent holes VH1 andVH2 may be positioned between the external terminals 150. The vent holesVH1 and VH2 may each have a width of about 100 μm to about 300 μm.

The first vent holes VH1 may be disposed spaced apart from each otherWhen viewed in a plan view, the first vent holes VH1 may be arranged ata regular interval. As shown in FIG. 11 , the first vent holes VH1 maybe arranged in the second direction D2. In some example embodiments, asshown in FIG. 12 , the first vent holes VH1 may be arranged along thefirst and second directions D1 and D2. In this case, when viewed in aplan view, the first vent holes VH1 may constitute at least one columnand at least one row. For example, the first vent holes VH1 may bearranged in a cross shape, a tetragonal lattice shape (or grid shape),or a hexagonal lattice shape (or honeycomb shape).

The second vent holes VH2 may be disposed spaced apart from each otherWhen viewed in a plan view, the second vent holes VH2 may be arranged ata regular interval. The second vent holes VH2 may be arranged along alateral surface of the first semiconductor chip 200. For example, asshown in FIGS. 11 and 12 , the second vent holes VH2 may be arranged inthe second direction D2. For another example, the second vent holes VH2may be arranged in a grid shape having a plurality of columns and rowsalong the first and second directions D1 and D2.

The present inventive concepts, however, are not limited thereto, andthe vent holes VH1 and VH2 may be arranged in various shapes. Inaddition, the vent holes VH1 and VH2 may be arranged at an irregularperiod. For example, the vent holes VH1 and VH2 may be provided to haveno specific regularity. According to some example embodiments, eitherthe first vent holes VH1 or the second vent holes VH2 may be omitted.

The molding layer 400 may fill a space between the package substrate 100and the first semiconductor chip 200. A portion of the molding layer 400may extend onto a bottom surface of the package substrate 100 from thespace between the package substrate 100 and the first semiconductor chip200. The molding layer 400 may have an extension at its portion formedof a molding member that flows through the vent holes VH1 and VH2 ontothe bottom surface of the package substrate 100. The molding layer 400may extend from the space between the package substrate 100 and thefirst semiconductor chip 200 through the vent holes VH1 and VH2 of thepackage substrate 100 onto the bottom surface of the package substrate100. The molding layer 400, as shown in FIG. 10 , may entirely cover thebottom surface of the package substrate 100. In this case, the moldinglayer 400 may serve as a passivation layer that protects the bottomsurface of the package substrate 100. In some example embodiments, themolding layer 400 may cover a portion of the bottom surface of thepackage substrate 100. A planar shape of the molding layer 400 on thebottom surface of the package substrate 100 may depend on thearrangement of the vent holes VH1 and VH2. For example, when the ventholes VH1 and VH2 are arranged along the second direction D2 as shown inFIG. 11 , the molding layer 400 on the bottom surface of the packagesubstrate 100 may have a linear shape that extends in the seconddirection D2. For another example, when the vent holes VH1 and VH2 arearranged along the first and second directions D1 and D2, the moldinglayer 400 on the bottom surface of the package substrate 100 may have ashape that extends in the first and second directions D1 and D2 (e.g., across or grid shape in the case of FIG. 12 ).

FIG. 13 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts.

Referring to FIG. 13 , a third semiconductor chip 600 may be disposed onthe first semiconductor chip 200. The third semiconductor chip 600 maybe disposed on the rear surface of the first semiconductor chip 200. Thethird semiconductor chip 600 and the first semiconductor chip 200 may bedisposed in an offset stack structure. For example, the firstsemiconductor chip 200 and the third semiconductor chip 600 may bestacked obliquely in a direction reverse to the first direction D1,which may result in an ascending stepwise shape. In some exampleembodiments, a portion of the third semiconductor chip 600 may overlapthe first semiconductor chip 200, and another portion of the thirdsemiconductor chip 600 may protrude beyond one lateral surface of thefirst semiconductor chip 200. The third semiconductor chip 600 mayprotrude beyond the second lateral surface 200 b of the firstsemiconductor chip 200. For example, when viewed in a plan view, thethird semiconductor chip 600 may be stacked on the first semiconductorchip 200 such that the third semiconductor chip 600 may be shifted(e.g., offset) from the first semiconductor chip 200 in a directionreverse to the first direction D1. A front surface, or a bottom surface,of the third semiconductor chip 600 may be parallel or substantiallyparallel to the top surface of the package substrate 100.

The third semiconductor chip 600 may be configured identical orsubstantially identical or similar to the second semiconductor chip 300.For example, the third semiconductor chip 600 may be of the same type asthe second semiconductor chip 300. For example, the third semiconductorchip 600 may be a memory chip, such as dynamic random-access memory(DRAM), static random access memory (SRAM), magnetic random accessmemory (MRAM), or Flash memory. In some example embodiments, the thirdsemiconductor chip 600 may be a logic chip, a passive device, or anyother suitable semiconductor chip. The third semiconductor chip 600 mayinclude a semiconductor material, such as silicon (Si). For example, thethird semiconductor chip 600 may include a third base layer 601 where isformed a third integrated circuit 602 of the third semiconductor chip600, and may also include a third chip wiring layer 610 disposed on onesurface on which the third integrated circuit 602 is formed in the thirdbase layer 601. The third chip wiring layer 610 may include a third chipdielectric pattern, a third chip wiring pattern 614 in the third chipdielectric pattern, third chip pads 616 connected to the third chipwiring pattern 614, and a third chip passivation layer that encapsulatesthe third chip wiring pattern 614 and the third chip pads 616 on thethird chip dielectric pattern and exposes the third chip pads 616.

The third semiconductor chip 600 may further include a secondredistribution layer 650 provided on the front surface of the thirdsemiconductor chip 600. For example, the second redistribution layer 650may be provided on the bottom surface of the third semiconductor chip600, and may cover the third base layer 601 and the third chip wiringlayer 610. The second redistribution layer 650 may include a seconddielectric pattern 652 stacked on the bottom surface of the thirdsemiconductor chip 600, a second wiring pattern 654 provided in thesecond dielectric pattern 652, and second signal pads 656 and seconddummy pads 658 exposed on a bottom surface of the second redistributionlayer 650.

The third semiconductor chip 600 may be flip-chip mounted on the packagesubstrate 100. For example, second connection terminals 390 may beprovided between the second signal pads 656 and the package substrate100. The third semiconductor chip 600 may be connected to the packagesubstrate 100 through the second signal pads 656, the second connectionterminals 390, and the substrate wiring pattern 120. The secondconnection terminals 390 may be disposed on one side in a directionreverse to the direction D1 from the first semiconductor chip 200. Forexample, the second connection terminals 390 may be disposed adjacent tothe second lateral surface 200 b of the first semiconductor chip 200.The second connection terminals 390 may be correspondingly provided onthe second signal pads 656. An arrangement of the second connectionterminals 390 may conform to that of the second signal pads 656. Forexample, the second connection terminals 390 may constitute at least onecolumn that extends along the second direction D2. The second connectionterminals 390 may be coupled to the substrate wiring pattern 120 of thepackage substrate 100. Therefore, the third integrated circuit 602 ofthe third semiconductor chip 600 may be electrically connected to thepackage substrate 100 through the second redistribution layer 650, thesecond signal pads 656, and the second connection terminals 390. Thesecond connection terminals 390 may include a solder ball or a solderbump. For example, the second connection terminals 390 may be solderballs each having a composite structure that includes a core portionformed of metal and a peripheral portion surrounding the core portion.

According to some example embodiments of the present inventive concepts,as the second and third semiconductor chips 300 and 600 are disposed tovertically overlap the first semiconductor chip 200, the first, second,and third semiconductor chips 200, 300, and 600 may have a reducedoccupying planar area and a compact-sized semiconductor package may beprovided.

FIG. 14 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts.

Referring to FIG. 14 , a fourth semiconductor chip 700 may be disposedon the package substrate 100. The fourth semiconductor chip 700 may behorizontally spaced apart from the first semiconductor chip 200. Thefourth semiconductor chip 700 may be disposed on one side in the firstdirection D1 of the first semiconductor chip 200. In this case, thefirst connection terminals 380 may be provided between the firstsemiconductor chip 200 and the fourth semiconductor chip 700.

The fourth semiconductor chip 700 may be configured identical orsubstantially identical or similar to the first semiconductor chip 200.For example, the fourth semiconductor chip 700 may be of the same typeas the first semiconductor chip 200. For example, the fourthsemiconductor chip 700 may be a memory chip, such as dynamicrandom-access memory (DRAM), static random access memory (SRAM),magnetic random access memory (MRAM), or Flash memory. In some exampleembodiments, the fourth semiconductor chip 700 may be a logic chip, apassive device, or any other suitable semiconductor chip. The fourthsemiconductor chip 700 may include a semiconductor material, such assilicon (Si). For example, the fourth semiconductor chip 700 may includea fourth base layer 701 where is formed a fourth integrated circuit 702of the fourth semiconductor chip 700, and may also include a fourth chipwiring layer 710 disposed on one surface on which the fourth integratedcircuit 702 is formed in the fourth base layer 701. The fourth chipwiring layer 710 may include a fourth chip dielectric pattern, a fourthchip wiring pattern 714 in the fourth chip dielectric pattern, fourthchip pads 716 connected to the fourth chip wiring pattern 714, and afourth chip passivation layer that encapsulates the fourth chip wiringpattern 714 and the fourth chip pads 716 on the fourth chip dielectricpattern and exposes the fourth chip pads 716 The fourth chip pads 716may include a metallic material, such as aluminum (Al).

The fourth semiconductor chip 700 may be flip-chip mounted on thepackage substrate 100. For example, the fourth semiconductor chip 700may be disposed to allow the fourth chip pads 716 to face the packagesubstrate 100. A plurality of second chip terminals 720 may be providedbetween the fourth chip pads 716 and the package substrate 100. Thesecond chip terminals 720 may penetrate the fourth passivation layer andmay be coupled to the fourth chip pads 716. The fourth semiconductorchip 700 may be connected to the package substrate 100 through thefourth chip pads 716, the second chip terminals 720, and the substratewiring pattern 120.

The second semiconductor chip 300 may be disposed on the firstsemiconductor chip 200 and the fourth semiconductor chip 700. The secondsemiconductor chip 300 may be positioned on the rear surface of thefirst semiconductor chip 200 and a rear surface of the fourthsemiconductor chip 700. The second semiconductor chip 300 may have oneportion that overlaps the first semiconductor chip 200 and anotherportion that overlaps the fourth semiconductor chip 700. The secondsemiconductor chip 300 may have a central portion that is positionedbetween the one portion and the another portion of the secondsemiconductor chip 300, and the central portion of the secondsemiconductor chip 300 may be located on the first connection terminals380.

The second semiconductor chip 300 may be flip-chip mounted on thepackage substrate 100. For example, the second semiconductor chip 300may be disposed to allow the first signal pads 356 of the firstredistribution layer 350 to face the package substrate 100. The secondsemiconductor chip 300 may be connected to the package substrate 100through the second chip pads 316, the first signal pads 356, and thesubstrate wiring pattern 120.

The first dummy pads 358 may be provided between the secondsemiconductor chip 300 and the rear surface of the first semiconductorchip 200 and between the second semiconductor chip 300 and the rearsurface of the fourth semiconductor chip 700. The first dummy pads 358may support the second semiconductor chip 300 on the rear surface of thefirst semiconductor chip 200 and on the rear surface of the fourthsemiconductor chip 700. Each of the first dummy pads 358 may be indirect contact with the rear surface of the first semiconductor chip 200or the rear surface of the fourth semiconductor chip 700.

According to some example embodiments of the present inventive concepts,as the second semiconductor chip 300 is disposed to vertically overlapthe first and fourth semiconductor chips 200 and 700, a semiconductorpackage may be provided to have a compact size. In addition, as thesecond semiconductor chip 300 is supported by both of the first andfourth semiconductor chips 200 and 700, a semiconductor package mayincrease in structural stability.

FIG. 15 illustrates a cross-sectional view showing a semiconductorpackage according to some example embodiments of the present inventiveconcepts.

Referring to FIG. 15 , a package substrate 100 may be provided thereonwith a first chip stack ST1 and a second chip stack ST2.

The package substrate 100 may include one or more substrate wiringlayers that are stacked on each other. Each of the substrate wiringlayers may include a substrate dielectric layer 110 and a substratewiring pattern 120 in the substrate dielectric layer 110.

Each of the first and second chip stacks ST1 and ST2 may include a firstsemiconductor chip 200 mounted on the package substrate 100, a secondsemiconductor chip 300 on the first semiconductor chip 200, and firstconnection terminals 380 that connect the second semiconductor chip 300to the package substrate 100.

The first semiconductor chip 200, the second semiconductor chip 300, andthe first connection terminals 380 may be configured identical orsimilar to those discussed with reference to FIGS. 1 to 9 . For example,the first semiconductor chips 200 may be flip-chip mounted on thepackage substrate 100. The first semiconductor chips 200 may be providedthereon with the second semiconductor chip 300 that are horizontallyshifted from the first semiconductor chips 200. For example, one of thefirst semiconductor chip 200 and one of the second semiconductor chips300 may be disposed in an offset stack structure, and each of the offsetstack structures may correspond to either the first chip stack ST1 orthe second chip stack ST2. The second semiconductor chips 300 may beconfigured identical or substantially identical to the firstsemiconductor chips 200, and may further include their firstredistribution layers 350 compared to the first semiconductor chips 200.The first redistribution layer 350 may include a first dielectricpattern 352 stacked on the bottom surface of the second semiconductorchip 300, a first wiring pattern 354 provided in the first dielectricpattern 352, and first signal pads 356 and first dummy pads 358 exposedon a bottom surface of the first redistribution layer 350. A pluralityof first connection terminals 380 may be provided between the firstsignal pads 356 and the package substrate 100. The second semiconductorchip 300 may be connected to the package substrate 100 through the firstsignal pads 356, the first connection terminals 380, and the substratewiring pattern 120.

The first chip stack ST1 and the second chip stack ST2 may be spacedapart from each other on the package substrate 100. The first chip stackST1 and the second chip stack ST2 may be disposed to allow the secondlateral surfaces 200 b of the first semiconductor chip 200 to face eachother. For example, the first semiconductor chips 200 may be disposed onthe central portion of the package substrate 100, and the firstconnection terminals 380 may be disposed on an outer portion of thepackage substrate 100. An interval between the first and second chipstacks ST1 and ST2 may range from about 100 μm to about 300 μm. Forexample, a range of about 100 μm to about 300 μm may be given as aninterval between the second lateral surfaces 200 b of the firstsemiconductor chips 200 of the first and second chip stacks ST1 and ST2.

The package substrate 100 may have third vent holes VH3 (e.g., may haveinner surfaces 100S3 that define the third vent holes WH3 extendingthrough the thickness of the package substrate 100). The third ventholes VH3 may vertically penetrate the package substrate 100 to extendfrom the top to bottom surfaces of the package substrate 100. The thirdvent holes VH3 may be provided on the central portion of the packagesubstrate 100. When viewed in a plan view, the third vent holes VH3 maybe positioned between the first semiconductor chips 200. In some exampleembodiments, although not shown, vent holes may be additionally providedbelow the first semiconductor chips 200 or below the secondsemiconductor chips 300. The third vent holes VH3 may each have a widthof about 100 μm to about 300 μm.

A molding layer 400 may be provided on the package substrate 100. Themolding layer 400 may cover the first chip stack ST1 and the second chipstack ST2. The molding layer 400 may extend from the package substrate100 through the third vent holes VH3 of the package substrate 100 ontothe bottom surface of the package substrate 100.

FIGS. 16, 17, 18, 19, 20, 21, and 22 illustrate cross-sectional viewsshowing a method of fabricating a semiconductor package according tosome example embodiments of the present inventive concepts.

Referring to FIG. 16 , there may be formed first and secondsemiconductor chips 200 and 300 of FIG. 1 . FIG. 16 depicts theformation of the first semiconductor chip 200 or the secondsemiconductor chip 300, and it is assumed that the first and secondsemiconductor chips 200 and 300 are of the same type as each other. Thefirst semiconductor chip 200 may be same as that discussed withreference to FIGS. 1 to 5 . For example, integrated circuits 1002 may beformed on a semiconductor wafer 1000. The semiconductor wafer 1000 mayhave a top surface as an active surface. A chip wiring layer 1010 may beformed on the top surface of the semiconductor wafer 1000. For example,the formation of the chip wiring layer 1010 may include forming adielectric pattern on the active surface of the semiconductor wafer1000, forming a wiring pattern 1014 that penetrates the dielectricpattern and connect with the integrated circuits 1002, forming on thedielectric pattern a plurality of chip pads 1016 that are connected tothe wiring pattern 1014, forming on the dielectric pattern a passivationlayer that covers the chip pads 1016, and patterning the passivationlayer to form openings OP that partially expose top surfaces of the chippads 1016. The chip pads 1016 may correspond to the first chip pads (see216 of FIG. 1 ) of the first semiconductor chip 200 or the second chippads (see 316 of FIG. 1 ) of the second semiconductor chip 300.

Afterwards, the semiconductor wafer 1000 may undergo a singulationprocess performed along a first sawing line SL1, and may thus beseparated into the first semiconductor chips 200.

Referring to FIG. 17 , a redistribution layer 1050 may be formed beforethe singulation process is performed on the semiconductor wafer 1000 ofFIG. 16 . For example, a conductive material may be coated on the topsurface of the semiconductor wafer 1000 or a top surface of the chipwiring layer 1010, and the coated conductive material may be patternedto form a wiring pattern 1054. The wiring pattern 1054 may penetrate theopenings (see OP of FIG. 16 ) and may be coupled to the chip pads 1016.The chip wiring layer 1010 may be coated thereon with a dielectricmaterial to form a dielectric pattern 1052 that encapsulates the wiringpattern 1054. In some example embodiments, the chip wiring layer 1010may be coated on its top surface with a dielectric material to form thedielectric pattern 1052, and then the wiring pattern 1054 may be formedto penetrate the dielectric pattern 1052 and the passivation layer andmay be coupled to the chip pads 1016. The formation of the wiringpattern 1054 and the formation of the dielectric pattern 1052 may berepeatedly performed to form wiring layers that are stacked on eachother. After that, signal pads 1056 and dummy pads 1058 may be formed onthe dielectric pattern 1052, thereby being coupled to the wiring pattern1054. For example, the dielectric pattern 1052 may be patterned to formholes that expose the wiring pattern 1054, a metal layer may be formedon the dielectric pattern 1052, and then the metal layer may bepatterned to form the signal pads 1056 that are coupled through theholes to the wiring pattern 1054 and to form the dummy pads 1058 thatare disposed on a top surface of the dielectric pattern 1052. The signalpads 1056 and the dummy pads 1058 may be components formed in oneprocess. The signal pads 1056 and the dummy pads 1058 may have their topsurfaces located at the same level from the top surface of thesemiconductor wafer 1000. The redistribution layer 1050 may correspondto the first redistribution layer (see 350 of FIG. 1 ) of the secondsemiconductor chip 300. For example, the dielectric pattern 1052 maycorrespond to the first dielectric pattern (see 352 of FIG. 2 ) of thefirst redistribution layer 350, the wiring pattern 1054 may correspondto the first wiring pattern (see 354 of FIG. 2 ) of the firstredistribution layer 350, the signal pads 1056 may correspond to thefirst signal pads (see 356 of FIG. 2 ) of the first redistribution layer350, and the dummy pads 1058 may correspond to the first dummy pads (see358 of FIG. 2 ) of the first redistribution layer 350.

Afterwards, the semiconductor wafer 1000 may undergo a singulationprocess performed along the first sawing line SL1, and may thus beseparated into the second semiconductor chips 300.

Referring to FIG. 18 , a carrier substrate 2000 may be provided. Thecarrier substrate 2000 may be a dielectric substrate including glass orpolymer, or may be a conductive substrate including metal. Although notshown, the carrier substrate 2000 may be provided with an adhesivemember on a top surface of the carrier substrate 2000. For example, theadhesive member may include a glue tape.

A package substrate 100 may be formed on the carrier substrate 2000. Thefollowing will describe in detail the formation of the package substrate100.

A lower dielectric layer 2100 may be provided on the carrier substrate2000. The lower dielectric layer 2100 may include a dielectric polymeror a photosensitive polymer.

A plurality of external pads 130 may be formed in the lower dielectriclayer 2100. For example, the lower dielectric layer 2100 may bepatterned to form openings for forming the external pads 130, a seedlayer may be conformally formed in the openings, and then performing anelectroplating process in which the seed layer is used as a seed to formthe external pads 130 that fill the openings.

A substrate dielectric layer 110 may be formed on the lower dielectriclayer 2100. The substrate dielectric layer 110 may be formed by acoating process such as spin coating or slit coating. The substratedielectric layer 110 may include a photo-imageable dielectric (PID). Forexample, the photo-imageable dielectric polymer may include at least oneselected from photosensitive polyimide, polybenzoxazole (PBO), phenolicpolymers, and benzocyclobutene polymers.

A substrate wiring pattern 120 may be formed. For example, the substratedielectric layer 110 may be patterned to form openings that expose theexternal pads 130, a barrier layer and a conductive layer may be formedon the substrate dielectric layer 110 so as to fill the openings, andthen the barrier layer and the conductive layer may undergo aplanarization process to form the substrate wiring pattern 120. Asubstrate wiring layer may be formed which includes the substratedielectric layer 110 and the substrate wiring pattern 120. The formationof the substrate wiring layer may be repeated to form the packagesubstrate 100 in which the substrate wiring layers are stacked. Thesubstrate wiring pattern 120 of an uppermost substrate wiring layer maycorrespond to a substrate pad of the package substrate 100.

Referring to FIG. 19 , the first semiconductor chips 200 may be mountedon the package substrate 100. For example, solder balls may be providedon the first chip pads 216 of the first semiconductor chips 200. Thefirst semiconductor chips 200 may be positioned on the package substrate100 so as to allow the first chip pads 216 to align with the substratewiring pattern 120 of the package substrate 100. After that, the firstsemiconductor chips 200 may descend to allow the solder balls to contactthe substrate wiring pattern 120, and then the solder ball may undergo areflow process to form first chip terminals 220 that connect the firstsemiconductor chip 200 to the package substrate 100.

Referring to FIG. 20 , the second semiconductor chips 300 may beprovided on the package substrate 100. For example, solders 385 may beprovided on the substrate wiring pattern 120 positioned on one side ofeach of the first semiconductor chips 200. The solders 385 may becoupled to the substrate wiring pattern 120. The solders 385 may havetheir top ends located at a level the same as or higher than that of atop surface of the first semiconductor chip 200. The solders 385 mayinclude a solder ball or a solder bump. For example, the solders 385 maybe solder balls each having a composite structure that includes a coreportion formed of metal and a peripheral portion surrounding the coreportion.

According to some example embodiments of the present inventive concepts,the solders 385 may each include therein the core portion whose meltingpoint is high, and on the substrate wiring pattern 120, the core portionmay support the peripheral portion. Even when the solders 385 have theirlarge heights, the core portions may prevent the solders 385 or theperipheral portions from running down or collapse toward one side.

The second semiconductor chip 300 may be positioned on the packagesubstrate 100 to allow the first signal pads 356 to align with thesolders 385, which first signal pads 356 are included in the firstredistribution layer 350 of the second semiconductor chip 300.

Referring to FIG. 21 , the second semiconductor chip 300 may descend toallow the first signal pads 356 to contact the solders 385, and then thesolders 385 may undergo a reflow process to form first connectionterminals 380 that connect the second semiconductor chip 300 to thepackage substrate 100. The first connection terminals 380 may cause thesecond semiconductor chip 300 and the package substrate 100 to connectwith each other on one side of the first semiconductor chip 200.

According to some example embodiments of the present inventive concepts,as the core portions of the solders 385 support the peripheral portionson the substrate wiring pattern 120, even though a large distance isprovided between the package substrate 100 and the second semiconductorchip 300, the second semiconductor chip 300 may be easily mounted on thepackage substrate 100.

Referring to FIG. 22 , a molding layer 400 may be formed on the packagesubstrate 100. For example, the package substrate 100 may be coated onits top surface with a molding material to encapsulate the first andsecond semiconductor chips 200 and 300, and the molding material may becured to form the molding layer 400. The molding layer 400 may fill aspace between the package substrate 100 and the second semiconductorchip 300.

The carrier substrate 2000 may be removed. The removal of the carriersubstrate 2000 may expose a bottom surface of the package substrate 100or may expose the external pads 130 of the package substrate 100.

Referring back to FIG. 1 , the lower dielectric layer 2100 may beremoved, and a substrate protection layer 140 may be formed below thepackage substrate 100. Below the substrate dielectric layer 110, thesubstrate protection layer 140 may cover the substrate wiring pattern120 and the external pads 130. In some example embodiments, a dielectricmaterial layer may be additionally coated on the lower dielectric layer2100. The lower dielectric layer 2100 and the dielectric material layermay form the substrate protection layer 140.

The substrate protection layer 140 may be patterned to expose theexternal pads 130. The external pads 130 may be provided thereon withexternal terminals 150. As such, it may be possible to fabricate asemiconductor package discussed with reference to FIG. 1 .

Afterwards, as shown in FIG. 22 , the package substrate 100 may undergoa singulation process performed along a second sawing line SL2, and maythus be separated into a plurality of semiconductor packages.

Depending on necessity, the singulation process may be performed priorto the removal of the carrier substrate 2000 and the lower dielectriclayer 2100. For example, the carrier substrate 2000 may undergo asingulation process performed along the second sawing line SL2, whichmay result in separation of the package substrates 100, the first andsecond semiconductor chips 200 and 300, and the molding layers 400.

A semiconductor package according to some example embodiments of thepresent inventive concepts may be configured such that semiconductorchips may be disposed to vertically overlap each other to reduce an areathat the semiconductor chips occupy when viewed in a plan view, with theresult that the semiconductor package may become small in size. Aredistribution layer may be used to form the semiconductor packagehaving a large overlapping area between the semiconductor chips, and thesemiconductor package may decrease in planar area. Therefore, thesemiconductor package may become small in size.

In addition, the redistribution layer may increase the degree of freedomof electrical connection of an upper semiconductor chip, and there maybe a reduced length of electrical connection between a package substrateand the semiconductor chips. Accordingly, the semiconductor package mayincrease in electrical properties.

Moreover, dummy pads may be used to support the upper semiconductor chipon a lower semiconductor chip, and thus the semiconductor package mayhave improved structural stability.

Although the present inventive concepts have been described inconnection with some example embodiments of the present inventiveconcepts illustrated in the accompanying drawings, it will be understoodby one of ordinary skill in the art that variations in form and detailmay be made therein without departing from the spirit and essentialfeature of the present inventive concepts. The above disclosed exampleembodiments should thus be considered illustrative and not restrictive.

1. A semiconductor package, comprising: a first semiconductor chip on apackage substrate; a second semiconductor chip on the firstsemiconductor chip, the second semiconductor chip having aredistribution layer on a bottom surface of the second semiconductorchip; a plurality of under-bump pads on a bottom surface of theredistribution layer; a plurality of first solders adjacent to the firstsemiconductor chip, the first solders connecting a plurality of firstpads of the under-bump pads to a plurality of substrate pads of thepackage substrate; and a molding layer on the package substrate, themolding layer covering the first semiconductor chip, the secondsemiconductor chip, and the first solders, wherein a plurality of secondpads of the under-bump pads are in direct contact with a top surface ofthe first semiconductor chip, wherein the first pads are connectedthrough the redistribution layer to an integrated circuit of the secondsemiconductor chip, and wherein the second pads are insulated from theintegrated circuit of the second semiconductor chip.
 2. Thesemiconductor package of claim 1, wherein the redistribution layerincludes: a dielectric pattern that covers the bottom surface of thesecond semiconductor chip and a plurality of first chip pads of thesecond semiconductor chip; and a wiring pattern in the dielectricpattern, the wiring pattern being coupled to the first chip pads andelectrically connected to the integrated circuit of the secondsemiconductor chip, wherein the first pads penetrate the dielectricpattern and are coupled to the wiring pattern.
 3. The semiconductorpackage of claim 2, wherein the dielectric pattern separates the secondpads from the wiring pattern.
 4. The semiconductor package of claim 1,wherein the first pads are spaced apart from the first semiconductorchip when viewed in a plan view, and the second pads vertically overlapthe first semiconductor chip.
 5. The semiconductor package of claim 1,wherein the first semiconductor chip is coupled to the package substratethrough a plurality of second solders on a plurality of second chippads, the second chip pads being on a bottom surface of the firstsemiconductor chip.
 6. The semiconductor package of claim 5, wherein afirst height of the first solders is about 1.5 times to about 30 times asecond height of the second solders.
 7. The semiconductor package ofclaim 6, wherein the first height of the first solders is in a range ofabout 50 μm to about 300 μm, and the second height of the second soldersis in a range of about 10 μm to about 50 μm.
 8. The semiconductorpackage of claim 1, wherein bottom surfaces of the first pads and bottomsurfaces of the second pads are at a same level from the bottom surfaceof the second semiconductor chip.
 9. The semiconductor package of claim1, wherein the first semiconductor chip has a first lateral surface in afirst direction and a second lateral surface in a second direction thatintersects the first direction, the first and second lateral surfacesbeing in direct contact with each other, and when viewed in a plan view,the second semiconductor chip protrudes beyond the first lateral surfaceand does not protrude beyond the second lateral surface.
 10. Thesemiconductor package of claim 9, wherein a wiring pattern of theredistribution layer is connected to the integrated circuit of thesecond semiconductor chip in a window region on a top surface of theredistribution layer, the window region extends in the second directionon a central portion of the redistribution layer, and the first pads arearranged along the second direction on one side in the first directionfrom the window region.
 11. The semiconductor package of claim 1,wherein the first semiconductor chip has a first lateral surface in afirst direction and a second lateral surface in a second direction thatintersects the first direction, the first and second lateral surfacesbeing in direct contact with each other, and when viewed in a plan view,the second semiconductor chip protrudes beyond both of the first lateralsurface and the second lateral surface.
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 18. Asemiconductor package, comprising: a package substrate; a firstsemiconductor chip and a second semiconductor chip that are sequentiallystacked on the package substrate; a molding layer on the packagesubstrate, the molding layer covering the first semiconductor chip andthe second semiconductor chip; and a plurality of external terminals ona bottom surface of the package substrate, wherein the secondsemiconductor chip is offset from the first semiconductor chip in ahorizontal direction that is parallel to at least a top surface of thepackage substrate to vertically overlap a first lateral surface and asecond lateral surface of the first semiconductor chip, the first andsecond lateral surfaces being adjacent to each other, wherein the firstsemiconductor chip is on the package substrate through a plurality offirst solders on the bottom surface of the first semiconductor chip suchthat the plurality of first solders are between the first semiconductorchip and the package substrate, wherein the second semiconductor chip ison the package substrate through a plurality of second solders on thepackage substrate such that the plurality of second solders are betweenthe second semiconductor chip and the package substrate, the secondsolders being adjacent to the first lateral surface and the secondlateral surface of the first semiconductor chip and being spaced apartfrom the first semiconductor chip, and wherein the second semiconductorchip is supported on a top surface of the first semiconductor chip. 19.The semiconductor package of claim 18, further comprising: aredistribution layer on a bottom surface of the second semiconductorchip; and a plurality of first pads and a plurality of second pads,wherein both of the plurality of first pads and the plurality of secondpads are on a bottom surface of the redistribution layer, wherein thefirst pads are between the first semiconductor chip and the secondsemiconductor chip and are in direct contact with the top surface of thefirst semiconductor chip, and wherein the second pads are adjacent tothe first semiconductor chip and are connected through the secondsolders to the package substrate.
 20. The semiconductor package of claim19, wherein bottom surfaces of the first pads and bottom surfaces of thesecond pads are at a same level from the bottom surface of the secondsemiconductor chip.
 21. The semiconductor package of claim 19, whereinthe second pads are spaced apart from the first semiconductor chip whenviewed in a plan view, and the first pads vertically overlap the firstsemiconductor chip.
 22. The semiconductor package of claim 19, whereinthe second pads are connected through the redistribution layer to anintegrated circuit of the second semiconductor chip, and the first padsare insulated from the integrated circuit of the second semiconductorchip.
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 28. A semiconductor package, comprising: a substrate; a firstsemiconductor chip on the substrate; a second semiconductor chip on thefirst semiconductor chip and horizontally offset from the firstsemiconductor chip in a horizontal direction that is parallel to atleast a top surface of the substrate; a redistribution layer on a bottomsurface of the second semiconductor chip and connected to an integratedcircuit of the second semiconductor chip; a dummy pad between the firstsemiconductor chip and the second semiconductor chip and on a bottomsurface of the redistribution layer; a signal pad on one side of thefirst semiconductor chip and on the bottom surface of the redistributionlayer; a connection terminal on the one side of the first semiconductorchip and between the substrate and the second semiconductor chip; and amolding layer on the substrate and covering the first semiconductor chipand the second semiconductor chip, the molding layer filling both aspace between the substrate and the first semiconductor chip and a spacebetween the substrate and the second semiconductor chip, wherein theconnection terminal directly connects the signal pad to a substrate padof the substrate.
 29. The semiconductor package of claim 28, wherein thesecond semiconductor chip is shifted from the first semiconductor chipto vertically overlap a first lateral surface and a second lateralsurface of the first semiconductor chip, the first and second lateralsurfaces being adjacent to each other.
 30. The semiconductor package ofclaim 28, wherein a bottom surface of the dummy pad and a bottom surfaceof the signal pad are at a same level from the bottom surface of thesecond semiconductor chip.
 31. The semiconductor package of claim 28,wherein the signal pad is connected through the redistribution layer tothe integrated circuit of the second semiconductor chip, and the dummypad is insulated from the integrated circuit of the second semiconductorchip.
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